1. general description the tfa9812 is a high-ef?ciency bridge tied load (btl) stereo class-d audio ampli?er with a digital i 2 s audio input. it is available in a hvqfn48 package with exposed die paddle. the exposed die paddle technology enhances the thermal and electrical performances of the device. the tfa9812 features digital sound processing and audio power ampli?cation. it supports i 2 c control mode and legacy mode. in legacy mode i 2 c involvement is not needed because the key features are controlled by hardware pin connections. a continuous time output power of 2 12w(r l =8 w ,v ddp = 15 v) is supported without an external heat sink. due to the implementation of a programmable thermal foldback even for high supply voltages, higher ambient temperatures, and/or lower load impedances, the device operates without sound interrupting behavior. tfa9812 is designed in such a way that it starts up easily (no special power-up sequence required). it features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust. a modulation technique is applied for the tfa9812, which supports common mode choke approach (1 common mode choke only per btl ampli?er stage). this minimizes the number of external components. 2. features 2.1 general features n 3.3 v and 8 v to 20 v external power supply n high ef?ciency and low power dissipation n speaker outputs fully short circuit proof across load, to supply lines and ground n pop noise free at power-up/power-down and sample rate switching n low power sleep mode n overvoltage and undervoltage protection on the 8 v to 20 v power supply n undervoltage protection on the 3.3 v power supply n overcurrent protection (no audible interruptions) n overdissipation protection n thermally protected and programmable thermal foldback n clock error protection n i 2 c mode control or legacy mode (i.e. no i 2 c) control n four different i 2 c addresses supported n internal phase-locked loop (pll) without using external components tfa9812 btl stereo class-d audio ampli?er with i 2 s input rev. 02 22 january 2009 preliminary data sheet
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 2 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input n no high system clock required (pll is able to lock on bck) n no external heat sink required n 5 v tolerant digital inputs n supports dual coil inductor application n easy application and limited external components required 2.2 dsp features n digital parametric 10-band equalizer n digital volume control per channel n selectable +24 db gain boost n analog interface to digital volume control in legacy mode n digital clip level control n soft and hard mute n thermal foldback threshold temperature control n de-emphasis n output power limiting control n polarity switch n four pulse width modulation (pwm) switching frequency settings 2.3 audio data input interface format support n master or slave master clock (mclk), bit clock (bck) and word select (ws) signals n philips i 2 s, standard i 2 s n japanese i 2 s, most signi?cant bit (msb) justi?ed n sony i 2 s, least signi?cant bit (lsb) justi?ed n sample rates from 8 khz to 192 khz 3. applications n digital-in class-d audio ampli?er applications n crt and ?at-panel television sets n flat-panel monitors n multimedia systems n wireless speakers n docking stations for mp3 players
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 3 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 4. quick reference data [1] i p is the current through the analog supply voltage (v dda ) pin added to the current through the power supply voltage (v ddp ) pin. table 1. quick reference table unless speci?ed otherwise, v dda =v ddp =12v,v ssp1 =v ssp2 =0v,v dda(3v3) =v ddd(3v3) = 3.3 v, v ss1 =v ss2 = refd = refa = 0 v, t amb =25 c, r l =8 w ,f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter conditions min typ max unit general v dda analog supply voltage 81220v v ddp power supply voltage 81220v v dda(3v3) analog supply voltage (3.3 v) 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) 3.0 3.3 3.6 v i p supply current soft mute mode, with load, ?lter and snubbers connected [1] -3845ma sleep mode [1] - 160 270 m a i dda(3v3) analog supply current (3.3 v) operating mode i 2 s slave mode - 2 4 ma i 2 s master mode - 4 6 ma sleep mode v dda =v ddp = 12 v - 120 - m a v dda =v ddp = 1 v - 40 70 m a i ddd(3v3) digital supply current (3.3 v) operating mode i 2 s slave mode - 15 25 ma i 2 s master mode - 25 40 ma sleep mode; data = ws = bck = mclk = 0 v -430 m a p o(rms) rms output power continuous time output power per channel; thd = 10 %; r l =8 w v dda = v ddp = 12 v - 8.3 - w v dda = v ddp = 13.5 v - 10 - w v dda = v ddp = 15 v - 12 - w short time ( 10 s) output power per channel; thd = 10 %; r l =8 w v dda = v ddp = 17 v - 15 - w h po output power ef?ciency r l =8 w ; p o(rms) = 8.3 w - 88 - %
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 4 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 5. ordering information table 2. ordering information type number package name description version tfa9812hn hvqfn48 plastic thermal enhanced very thin quad ?at package; no leads; 48 terminals; body 7 7 0.85 mm sot619-8
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 5 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 6. block diagram fig 1. tfa9812 block diagram 15 16, 17 18, 19 10, 11 25 23, 24 26, 27 v ddp v ssp1 22 boot1p v ddp out1p v ssp2 boot1n out1n stab1 boot2p stab1 control logic 20, 21 driver high 12 13, 14 v ddp v ssp2 v ddp out2p v ssp2 boot2n out2n stab2 stab2 xtalin xtalout mclk references protection ovp uvp ocp otp odp wp cdelay diag 1 2 47 31 39 41 42 45 tfa9812 010aaa217 control logic driver high driver low driver low control logic control logic driver high driver low driver high driver low pwm controller pwm controller control interface register address hex 01 phased locked loop thermal foldback oscillator adc 10 34 35 36 37 38 powerup sda/ms gain 33 enable csel adsel2/plim2 adsel1/plim1 scl/sfor stabd refd staba refa 30 29 48 8 exposed die paddle v ss1 v ss2 46 45 44 bck ws data csel test1 test2 avol v ddd(3v3) v dda(3v3) v dda 743 32 40 3 6 9 28 clock protection lp ufp ofp ibp serial audio interface 10-band parametric equalizer volume control and soft mute inter- polation filter and de-emphasis power limiter gain
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 6 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input figure 1 shows the block diagram of the tfa9812. for a detailed description of the audio signal path see section 8.1 . 7. pinning information 7.1 pinning fig 2. pin con?guration, transparent top view table 3. pinning description tfa9812 pin symbol type description 1 xtalin i crystal oscillator input 2 xtalout o crystal oscillator output 3v dda(3v3) p analog supply voltage (3.3 v) 4 staba o 1.8 v analog stabilizer output 5 refa p analog reference voltage 6v dda p analog supply voltage (8 v to 20 v) 7 test1 i test signal input 1. for test purposes only (connect to v ss ) 8v ss1 p pcb ground reference 9 stab2 o decoupling of internal 11 v regulator for channel 2 drivers 10 v ssp2 p negative power supply voltage for channel 1 and channel 2 11 v ssp2 p negative power supply voltage for channel 1 and channel 2 12 boot2n o bootstrap high-side driver negative pwm output channel 2 13 out2n o negative pwm output channel 2 010aaa218 tfa9812hn boot1n v ssp2 boot2n v ssp1 v ssp2 v ssp1 stab2 stab1 v ss1 diag test1 cdelay v dda powerup refa avol staba enable v dda(3v3) gain xtalout csel xtalin adsel2/plim2 out2n out2n boot1p out2p out1p v ddp v ddp out1p out1p boot1p out1n out1n v ss2 mclk bck ws data test2 refd stabd v ddd(3v3) sda/ms scl/sfor adsel1/plim1 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 7 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14 out2n o negative pwm output channel 2 15 boot1p o bootstrap high-side driver positive pwm output channel 1 16 out1p o positive pwm output channel 1 17 out1p o positive pwm output channel 1 18 v ddp p positive power supply voltage (8 v to 20 v) 19 v ddp p positive power supply voltage (8 v to 20 v) 20 out2p o positive pwm output channel 2 21 out2p o positive pwm output channel 2 22 boot2p o bootstrap high-side driver positive pwm output channel 2 23 out1n o negative pwm output channel 1 24 out1n o negative pwm output channel 1 25 boot1n o bootstrap high-side driver negative pwm output channel 1 26 v ssp1 p negative power supply voltage for channel 1 and channel 2 27 v ssp1 p negative power supply voltage for channel 1 and channel 2 28 stab1 o decoupling of internal 11 v regulator for channel 1 drivers 29 diag o fault mode indication output (open-drain pin) 30 cdelay i timing reference 31 powerup i power-up pin to switch between sleep and other operational modes 32 avol i analog volume control (legacy mode) 33 enable i enable input to switch between 3-state and other operational modes 34 gain i gain selection input to select between 0 db and +24 db gain (legacy mode) 35 csel i control selection input to select between legacy mode (no i 2 c bus control) and i 2 c bus control 36 adsel2/plim2 i address selection in i 2 c mode input 2, power limiter selection input 2 in legacy mode 37 adsel1/plim1 i address selection in i 2 c mode input 1, power limiter selection input 1 in legacy mode 38 scl/sfor i i 2 c bus clock input in i 2 c mode, i 2 s serial data format selection input in legacy mode 39 sda/ms i/o i 2 c bus data input and output in i 2 c mode, master/slave selection input in legacy mode 40 v ddd(3v3) p digital supply voltage (3.3 v) 41 stabd o 1.8 v digital stabilizer output 42 refd p digital reference voltage 43 test2 i test signal input 2; for test purposes only (connect to v ss ) 44 data i i 2 s bus data input 45 ws i/o i 2 s bus word select input (i 2 s slave mode) or output (i 2 s master mode) 46 bck i/o i 2 s bus bit clock input (i 2 s slave mode) or output (i 2 s master mode) table 3. pinning description tfa9812 continued pin symbol type description
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 8 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8. functional description 8.1 general the tfa9812 is a high-ef?ciency stereo btl class-d ampli?er with a digital i 2 s audio input. it supports all commonly used i 2 s formats. figure 1 shows the functional block diagram, which includes the key function blocks of the tfa9812. in the digital domain the audio signal is processed and converted to a pulse width modulated signal using bd modulation. a btl con?gured power comparator carries out power ampli?cation. the audio signal processing path is as follows: 1. the digital audio input (dai) block translates the i 2 s (-like) input signal into a standard internal stereo audio stream. 2. the 10-band parametric equalizer can optionally equalize the stereo audio stream. both channels have separate equalization streams. it can be used for speaker transfer curve compensation to optimize the audio performance of applied speakers. 3. volume control in the tfa9812 is done by attenuation. the attenuation depends on the volume control settings and the thermal foldback value. soft mute is also arranged at this part. in legacy mode the volume control is done by an on-board analog-to-digital converter (adc) which measures the analog voltage on pin 32. 4. the interpolation ?lter interpolates from 1 fs to the pwm controller sample rate (2048 fs at 44.1 khz) by cascading fir ?lters. 5. the gain block can boost the signal with 0 db or +24 db. four speci?c gain settings are also provided in this block. these speci?c gain settings are related to maximum clip levels of < 0.5 %, 10 %, 20 % or 30 % thd at the tfa9812 output. these maximum clip levels are only valid with the gain boost set to 0 db an d a 0 dbfs input signal. 6. the power limiter limits the maximum output signal of the tfa9812. the power limiter settings are 0 db, - 1.5 db, - 3 db, and - 4.5 db. this function can be used to reduce the maximum output power delivered to the speakers at a ?xed supply voltage and speaker impedance. 7. the pwm controller block transforms the audio signal into a bd-modulated pwm signal. the bd-modulation provides a high signal-to-noise performance and eliminates clock jitter noise. 8. via four differential comparators the pwm signals are ampli?ed by two btl power output stages. by default the left audio signal is connected to channel 1 and the right audio signal to channel 2. 47 mclk i/o master clock input (i 2 s slave mode) or output (i 2 s master mode) 48 v ss2 p pcb ground reference exposed die-paddle - p pcb ground reference table 3. pinning description tfa9812 continued pin symbol type description
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 9 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input the block control de?nes the operational control settings of the tfa9812 in line with the actual i 2 c settings and the pin-controlled settings. the pll block creates the system clock and can take the i 2 s bck, the mclk or an external crystal as reference source. the following protections are built into the tfa9812: ? thermal foldback (tf) ? overtemperature protection (otp) ? overcurrent protection (ocp) ? overvoltage protection (ovp) ? undervoltage protection (uvp) ? window protection (wp) ? lock protection (lp) ? underfrequency protection (ufp) ? overfrequency protection (ofp) ? invalid bck protection (ibp) ? dc-blocking ? electrostatic discharge (esd) 8.2 functional modes 8.2.1 control modes the two control modes of the tfa9812 are i 2 c and legacy. ? in i 2 c mode the i 2 c format control is enabled. ? in legacy mode a pin-based subset of the control options is available. the control settings for features which are not available in legacy mode are set to the default i 2 c register settings. the control mode is selected via pin csel as shown in t ab le 4 . in the functional descriptions below the control for the various functions will be described for each control mode. section 9.6 summarizes the support given by each control mode for the various tfa9812 functions. 8.2.2 key operating modes there are six key operating modes: ? in sleep mode the voltage supplies are present, but power consumption for the whole device is reduced to the minimum level. the output stages in sleep mode are 3-state and i 2 c communication is disabled. table 4. control mode selection csel pin value control mode 0 legacy (no i 2 c) 1i 2 c
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 10 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input ? in soft mute mode the i 2 s input signal is overruled with a soft mute. C in legacy control mode the analog input pin avol controls soft mute mode. C in i 2 c control mode i 2 c control can be used to enable an automatic soft mute function. see also section 8.5.3 . ? in hard mute mode the pwm controller is overruled with a 50 % duty cycle square pulse. the hard mute mode is only available in i 2 c control mode. ? in operating mode the tfa9812 ampli?es the i 2 s audio input signal in line with the actual control setting. ? in 3-state mode the output stages are switched off. ? fault mode is entered when a fault condition is detected by one or more of the protection mechanisms implemented in the tfa9812. in fault mode the actual device con?guration depends on the fault detected: see section 8.7 for more information. fault mode is for a subset of the faults ?agged on the diag output pin. when the diag pin is ?agged the output stages will be forced to enter 3-state mode. in sleep mode the diag pin will not ?ag fault modes. [1] clocking faults do not trigger diag output. [2] under these conditions soft mute still has to be enabled by the appropriate i 2 c setting. 8.2.3 i 2 s master/slave modes and mclk/bck clock modes the i 2 s interface can be set in master or in slave. ? in i 2 s master mode the pll locks to the output signal of the internal crystal oscillator circuit which uses an external crystal. the bck, ws and mclk signals are generated by the tfa9812. on the mclk pin the tfa9812 delivers a master clock running at the crystal frequency. ? in i 2 s slave mode the pll can lock to: C the external mclk signal on the mclk pin called mclk clock mode. C the i 2 s input bck signal on the bck pin called bck clock mode. the i 2 s master or slave mode can be selected: ? in i 2 c control mode by selecting the right i 2 c setting. ? in legacy control mode by selecting the right setting on the sda/ms pin. table 5. operational mode selection pin: diag output operational mode selected: powerup enable csel avol 0 - - - ?oating sleep mode 1 - - - 0 / ?oating fault mode (enabled by system) [1] 1 1 1 - ?oating soft mute mode (in i 2 c control mode) [2] 1 1 0 < 0.8 v ?oating soft mute (in legacy control mode) 1 0 - - ?oating 3-state mode 1 1 - - ?oating operational mode
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 11 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] under these conditions the mode is enabled by the appropriate i 2 c setting. in i 2 s slave mode selection between bck and mclk clock modes is automatic. mclk clock mode is given higher priority than bck. if the mclk clock is judged valid by the protection circuit then mclk clock mode is enabled. bck clock mode is enabled when the mclk clock is invalid (e.g. not available) and the bck clock is judged valid by the protection circuit (see section 8.7.11 ). t ab le 7 shows the supported crystal frequencies in i 2 s master mode. t ab le 8 shows the supported mclk frequencies in mclk mode (i 2 s slave mode). t ab le 9 shows the supported bck frequencies in bck mode (i 2 s slave mode). table 6. i 2 s master/slave mode selection pin value clock mode i 2 s mode csel sda/ms 0 0 legacy slave 0 1 legacy master 1- i 2 c slave or master [1] table 7. valid crystal frequencies in i 2 s master mode control mode f s (khz) crystal frequency (mhz) i 2 c 8, 16, 32, 64, 128 8.192 11.025, 22.05, 44.1, 88.2, 176.4 11.2896 12, 24, 48, 96, 192 12.288 legacy 32 8.192 44.1 11.2896 48 12.288 table 8. valid mclk frequencies in i 2 s slave mode control mode f s (khz) mlck frequency (mhz) i 2 c 8, 16, 32, 64, 128 8.192 12.288 32 18.432 (576 f s ) 11.025, 22.05, 44.1, 88.2, 176.4 11.2896 16.9344 44.1 25.4016 (576 f s ) 12, 24, 48, 96, 192 12.288 18.432 48 27.648 (576 f s )
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 12 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] the valid sample frequencies are shown in section 9.5.7 . legacy 32 8.192 12.288 18.432 (576 f s ) 44.1 11.2896 16.9344 25.4016 (576 f s ) 48 12.288 18.432 27.648 (576 f s ) table 9. valid bck frequencies in i 2 s slave mode control mode f s (khz) bck (x f s input) i 2 c 8 to 192 [1] 32 f s 8 to 192 [1] 48 f s 8 to 192 [1] 64 f s legacy 32, 44.1, 48 32 f s 32, 44.1, 48 48 f s 32, 44.1, 48 64 f s table 8. valid mclk frequencies in i 2 s slave mode control mode f s (khz) mlck frequency (mhz)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 13 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8.3 power-up/power-down 8.3.1 power-up figure 3 and t ab le 10 describe the power-up timing while t ab le 11 shows the pin control for initiating a power-up reset. [1] mute in legacy mode is controlled by avol pin. fig 3. power-up/power-down timing external voltage supplies powerup pin i 2 c available enable pin pwm outputs t wake t d(on) t d(mute_off) t d(soft_mute) 010aaa219 soft mute setting in i 2 c mode avol pin in legacy mode operating mode active table 10. power-up/power-down timing symbol parameter conditions min typ max unit t wake wake-up time i 2 c control - 4 - ms t d(on) turn-on delay time - 70 - 135 ms t d(mute_off) mute off delay time - - - 128/f s s t d(soft_mute) soft mute delay time i 2 c control - - 128/f s s legacy control [1] -15-ms
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 14 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input in i 2 c control mode communication is enabled after 4 ms. the preferred i 2 c settings can be made within 66 ms before the pll starts running. finally, the output stages are enabled and the audio level is increased via a demute sequence if mute has previously been disabled. remark: in i 2 c mode soft mute is enabled by default. it can be disabled at any time while i 2 c communication is valid. in order to prevent audio clicks volume control (default setting is 0 db) should be set before soft mute is disabled. remark: for a proper start-up in i 2 s master mode and i 2 c mode the following sequence should be followed: 1. the i 2 s master setting should be set and keep the default sample rate setting active. 2. next, another sample rate setting than the default one should be selected. 3. finally, when the default sample rate is used the default sample rate setting should be selected again. 8.3.2 power-down figure 3 includes the power-down timing while t ab le 11 shows the pin control for enabling power-down. putting the tfa9812 into power-down is equivalent to enabling sleep mode (see section 8.2.2 ). this mode is entered immediately and no additional clock cycles are required. in order to prevent audible clicks, soft mute should be enabled at least t d(soft_mute) seconds before enabling sleep mode. the speci?ed low current and power conditions in t ab le 1 are valid within 10 m s after enabling sleep mode. 8.4 digital audio data input 8.4.1 digital audio data format support the tfa9812 supports a commonly used range of i 2 s and i 2 s-like digital audio data input formats. these are listed in t ab le 12 . table 11. power-up/power-down selection power-up pin value description 0 power-down (sleep mode) 1 power-up table 12. supported digital audio data formats bck frequency interface format (msb ?rst) supported in i 2 c control mode supported in legacy control mode 32 f s i 2 s up to 16-bit data yes yes 32 f s msb-justi?ed 16-bit data yes yes 32 f s lsb-justi?ed 16-bit data yes yes 48 f s i 2 s up to 24-bit data yes yes 48 f s msb-justi?ed up to 24-bit data yes yes
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 15 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input remark: only msb-?rst formats are supported. 48 f s lsb-justi?ed 16-bit data yes no 48 f s lsb-justi?ed 18-bit data yes no 48 f s lsb-justi?ed 20-bit data yes no 48 f s lsb-justi?ed 24-bit data yes yes 64 f s i 2 s up to 24-bit data yes yes 64 f s msb-justi?ed up to 24-bit data yes yes 64 f s lsb-justi?ed 16-bit data yes no 64 f s lsb-justi?ed 18-bit data yes no 64 f s lsb-justi?ed 20-bit data yes no 64 f s lsb-justi?ed 24-bit data yes no table 12. supported digital audio data formats bck frequency interface format (msb ?rst) supported in i 2 c control mode supported in legacy control mode fig 4. serial interface input and output formats 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb msb msb b2 2 1 12 3 left i 2 s-bus format ws bck data right 3 msb b2 010aaa458 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb 16 msb b2 b3 b4 left lsb-justified format 18 bits ws bck data right 15 18 17 2 1 msb b2 b3 b4 b17 lsb 16 15 18 17 2 1 b17 lsb msb-justified format ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 bck data
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 16 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input in i 2 c control mode the following sample frequency f s can be used: 8 khz, 11.025 khz, 12 khz, 16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, 48 khz, 64 khz, 88.2 khz, 96 khz, 128 khz, 176.4 khz or 192 khz. the i 2 c control for f s selection can be found in section 9.5.7 . in legacy control mode the following sample frequencies (f s ) can be used: 32 khz, 44.1 khz or 48 khz. 8.4.2 digital audio data format control the bck-to-ws and mclk-to-ws frequency ratios are automatically detected, so no control settings need to be con?gured for these. in i 2 c control mode all the formats listed in t ab le 12 are supported. the appropriate i 2 c controls for selecting the supported formats can be found in section 9 . in the legacy control mode only a subset of the supported formats can be used. these are shown in t ab le 12 and the required pin control is given in t ab le 13 . see section 8.2.1 for details of how to enable legacy control mode. 8.5 digital signal-processing features 8.5.1 equalizer 8.5.1.1 equalizer options the equalizer function can be bypassed and the equalizer can be con?gured to either a 5-band or 10-band function. these settings are for both audio channels simultaneously. there are 20 bands in the equalizer. these are distributed as follows: ? bands a1 to a5 are bands 1 to 5 of output 1 (used in 5-band and 10-band con?guration). ? bands b1 to b5 are bands 1 to 5 of output 2 (used in 5-band and 10-band con?guration). ? bands c1 to c5 are bands 6 to 10 of output 1 (used in 10-band con?guration only). ? bands d1 to d5 are bands 6 to 10 of output 2 (used in 10-band con?guration only). in i 2 c control mode each band can be con?gured separately using i 2 c register settings. in legacy control mode the equalizer is bypassed. 8.5.1.2 equalizer band function the shape of each parametric equalizer band is determined by the three ?lter parameters: ? (relative) center frequency . ? quality factor q. ? gain factor g. table 13. digital audio data format selection in legacy control mode scl/sfor pin value interface formats (msb-?rst) 0i 2 s 1 msb-justi?ed w 2 p f c f s () =
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 17 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input in the above equation f c is the center frequency and f s is the sample frequency. the de?nition of the quality factor is the center frequency divided by the 3 db bandwidth, see equation 1 . in parametric equalizers this is only valid when the gain is set very small ( - 30 db). (1) each band ?lter can be programmed to perform a band-suppression (g < 1) or a band-ampli?cation (g > 1) function around the center frequency. each band of the tfa9812 equalizer has a second-order regalia-mitra all-pass ?lter structure. the structure is shown in figure 5 . the transfer function of this all-pass ?lter is shown in equation 2 : (2) a(z) is the second-order ?lter structure. the transfer function of a(z) is shown in equation 3 : (3) the relationship between the programmable parameters k 0 , k 1 , and k 2 and the ?lter parameters g, w , q is shown in equation 4 and equation 5 . use equation 4 to calculate band suppression (g < 1) functions. (4) use equation 5 to calculate band ampli?cation (g 3 1) functions. fig 5. regalia ?lter ?ow-diagram q f c f 2 f 1 C ----------------- ; = f 1 : 20 10 a f 1 a f c -------- ? ? ?? log 3db f c f 1 > = f 2 : 20 10 a f 2 a f c -------- ? ? ?? log 3db f 2 f c > , = ? x(z) a(z) s y(z) + + + - 010aaa406 k 0 /2 hz () 12 1az () + () k 0 2 1az () C () + = az () k 1 k 2 1k 1 + () z 1 C z 2 C + + 1k 2 1k 1 + () z 1 C k 1 z 2 C + + -------------------------------------------------------------------------------- - = k 0 g = k 1 w cos C = k 2 2q g w sin C () 2q g w sin + () = g1 <
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 18 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input (5) the ranges of the tfa9812 parametric equalizer settings for each band are: ? the gain, g is from - 30 db to +12 db. ? the center frequency, f c is from 0.0004 * f s to 0.49 * f s . ? the quality factor q is from 0.001 to 8. using i 2 c control, ?lter coef?cients need to be entered for each ?lter stage to con?gure it as desired. figure 6 , figure 7 and figure 8 show some of the possible transfer functions of the equalizer bands. the relations are symmetrical for the suppression and ampli?cation functions. a skewing effect can be observed for the higher frequencies. different con?gurations are available for the same ?lter transfer function, thus allowing optimum numerical noise performance. the binary ?lter con?guration parameters t 1 and t 2 control the actual con?guration and should be chosen according to equation 6 . (6) a maximum of 12 db ampli?cation per equalizer stage can be achieved with respect to the input signal. each band of the equalizer is provided with a - 6 db ampli?cation, so in order to prevent numerical clipping for some ?lter settings with over 6 db of ampli?cation, band ?lters can be scaled by 0 db or - 6 db. for optimum numerical noise performance steps of - 6 db ampli?cation should be applied to the highest possible sections that are still within scale signal processing safeguards. band ?lters can be scaled with the binary parameters listed in t ab le 14 . 8.5.1.3 equalizer band control for compact representation with positive signed parameters, parameters k 1 and k 2 are introduced in equation 7 . the parameters k 0 , k 1 ', k 2 ', t 1 , t 2 and s must be combined in two 16-bit control words, word1 and word2, and must ?t within the representation given in t ab le 15 . parameters k 1 ' and k 2 ' are unsigned ?oating-point representations in equation 8 . table 14. equalizer scale factor coding s scale factor (db) 00 1 - 6 k 0 g = k 1 w cos C = k 2 2q w sin C () 2q w sin + () = g1 3 t 1 0 w <= p 2 1 w > p 2 ? = t 2 0k 2 >= 0 1k 2 < 0 ? ? =
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 19 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input (7) (8) in equation 8 , m is the unsigned mantissa and e the negative signed exponent. for example, in word2 bits [14:8] = [0111 010] represent k 2 ' = (7/2 4 ) 2 - 2 = 1.09375 10 - 1 . section 9.5.4 shows the i 2 c address locations of the controls for various bands of the equalizer. table 15. equalizer control word construction word section data word1 15 t 1 word1 [14:4] 11 mantissa bits of k 1 word1 [3:0] four exponent bits of k 1 word2 15 t 2 word2 [14:11] four mantissa bits of k 2 word2 [10:8] three exponents bits of k 2 word2 [7:1] k 0 word2 0 s fig 6. transfer functions for several quality factors q k 1 1k 1 C t 1 1 = 1k 1 + t 1 0 = ? ? = k 2 1k 2 C t 2 0 = 1k 2 + t 2 1 = ? ? = k x m2 e C m1 < = 010aaa222 4 8 12 gain (db) 0 frequency (hz) 10 1 10 5 10 4 10 2 10 3 q1 = 0.27 q2 = 0.61 q3 = 1.65
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 20 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8.5.2 digital volume control in i 2 c control mode both audio channels have separate digital volume control. in legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin avol (32). 8-bit volume control is available per channel. this is db-linear down to - 124 db in steps of 0.5 db. the last step of the volume control is mute. t ab le 16 shows the various settings and their related channel suppression: fig 7. transfer functions for several center frequencies f c fig 8. transfer functions for several gain factors g 010aaa223 frequency (hz) 10 1 10 5 10 4 10 2 10 3 4 8 12 gain (db) 0 010aaa224 frequency (hz) 10 1 10 5 10 4 10 2 10 3 0 -6 6 12 gain (db) -12
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 21 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input section 9 shows the i 2 c address locations for the digital gain control for both channels. in legacy mode the pin avol (32) can be used to control the volume. voltage levels of 0.8 v to 2.8 v correspond linearly to control values of 00h (0 db) to f9h (mute). see t ab le 16 . an external pull-up resistor connected to the v ddd(3v3) can be applied to provide a default volume of 0 db. pin avol has no function in i 2 c mode. 8.5.3 soft mute and mute soft mute is available in i 2 c and in legacy control modes: hard mute can be enabled only in i 2 c control mode. in i 2 c control mode the soft mute function smoothly reduces the gain setting for both channels to mute level over a duration of 128/f s seconds. the smooth shape is implemented as a raised cosine function. soft demute results in a similar gain increase. this implementation avoids audible plops. a different soft mute and soft demute function is implemented in legacy mode. this works via the analog gain control under the control of pin avol. the analog volume control input signal is ?rst-order low-pass ?ltered with a time constant of 10 ms in the digital domain. suddenly switching on or switching off volume by setting the control voltage to > 2.8 v or < 0.8 v respectively will result in a fading which lasts approximately 15 ms (switching between 0 v and 3.3 v at avol). in legacy mode the soft demute function that is part of the automatic power-up sequence is similar to the i 2 c mode soft demute function described above. the i 2 c control for the soft and hard mute functions can be found in section 9 . 8.5.4 output signal and word-select polarity control in i 2 c control mode the tfa9812 can switch the polarity of the stereo output signal. the effect is a 180 degree phase shift of both output signals. the tfa9812 also has the option of switching the polarity of the ws signal. without polarity inversion the left audio signal is connected to channel 1 and the right audio signal is connected to channel 2. the i 2 c control for the polarity switch can be found in section 9.5.1 . 8.5.5 gain boost and clip level control an additional gain boost of +24 db can be selected in the tfa9812. in legacy mode this feature can be selected with the gain pin, see t ab le 17 . table 16. volume control channel suppression table [7:0] control value (hexadecimal) gain (db) 00 0 01 - 0.5 ... steps of 0.5 db f7 - 123.5 f8 - 124 f9 mute
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 22 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input the i 2 c controls for selecting the +24 db gain can be found in section 9.5.6 . the gain pin has no function in i 2 c mode. the tfa9812 features also speci?c gain settings which are related to < 0.5 %, 10 %, 20 % or 30 % clipping at the output of the tfa9812. these clipping values are only valid under the following conditions: ? the volume control is set to 0 db. ? the gain boost is set to 0 db. ? a 0 dbfs i 2 s input signal is obtained. the i 2 c controls for selecting a speci?c clip level can be found in section 9.5.6 . in legacy mode the clip level is set to 10 %. 8.5.6 output power limiter output power can be limited to three discrete levels with respect to the maximum power. the maximum power output value is determined by the value of the high voltage supply. clipping levels (see section 8.5.5 ) still apply to the maximum levels of reduced output voltage swings. in i 2 c control mode the same output power limiting levels can be selected, see section 9.5.6 . in legacy control mode two pins can be used to select the output power limit level as shown in t ab le 18 . 8.5.7 pwm control for performance improvement the pwm switching frequency of the tfa9812 is dependent on: ? the sampling frequency, f s . ? the sampling frequency setting, f s (selected) (see section 9.5.7 ). ? the pwm switching frequency setting, f sw (selected) (see section 9.5.6 ). equation 9 shows the relationship between these settings and the pwm carrier frequency: (9) table 17. gain pin functionality gain pin value function 0 0 db gain 1 +24 db gain table 18. legacy mode output power limiter control pin value function adsel2/plim2 adsel1/plim1 0 0 maximum power 0 1 maximum power - 1.5 db 1 0 maximum power - 3.0 db 1 1 maximum power - 4.5 db f sw f s f s selected ) () ---------------------------- f sw selected () =
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 23 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input the selected pwm switching frequency is 400 khz by default and can be set to 350 khz, 700 khz and 750 khz in i 2 c control mode. in legacy mode 400 khz is the only option and this scales linearly if 32 khz or 48 khz is used as f s . remark: the selected sample frequency, f s (selected) must be equal to the sample frequency (f s ) in i 2 c control mode. remark: the performance of am radio reception can sometimes be improved by selecting non-interfering frequencies for the pwm signal. 8.6 class-d ampli?cation the class-d power ampli?cation of the pwm signal is carried out in two btl power stages. the output signal voltage level is determined by the values on the v ddp pins. the power ampli?ers can be explicitly put into 3-state mode by using the pin enable as shown in t ab le 19 . the enable pin is functional in legacy mode and in i 2 c mode. [1] can be overruled by a forced 3-state in sleep or fault mode. 8.7 protection mechanisms the tfa9812 has a wide range of protection mechanisms to facilitate optimal and safe application. all of these are active in both i 2 c and legacy control modes. the following protections are included in the tfa9812: ? thermal foldback (tf) ? overtemperature protection (otp) ? overcurrent protection (ocp) ? overvoltage protection (ovp) ? undervoltage protection (uvp) ? window protection (wp) ? lock protection (lp) ? underfrequency protection (ufp) ? overfrequency protection (ofp) ? invalid bck protection (ibp) ? dc-blocking ? esd the reaction of the device to the different fault conditions differs per protection. table 19. enable pin functionality enable pin value function 0 output stages in 3-state mode. 1 switching enabled [1] .
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 24 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8.7.1 thermal foldback if the junction temperature of the tfa9812 exceeds the programmable thermal foldback threshold temperature the gain of the ampli?er is decreased gradually to a level where the combination of dissipation (p) and the thermal resistance from junction to ambient (r th(j-a) ) results in a junction temperature around the threshold temperature. this means that the device will not completely switch off, but remains operational at lower output power levels. especially with music output signals this feature enables high peak output power while still operating without any external heat sink other than the printed-circuit board area. if the junction temperature still increases due to external causes, the otp switches the ampli?er to 3-state mode. under i 2 c control the thermal foldback threshold temperature value can be lowered (see section 9.5.8 ): in legacy control mode the default threshold value of 125 c is ?xed. 8.7.2 overtemperature protection this is a hard protection to prevent heat damage to the tfa9812. the overtemperature threshold level is the 160 c junction temperature. when the threshold temperature is exceeded the output stages are set to 3-state mode. the temperature is then checked at 1 m s intervals and the output stages will operate normally again once the temperature has dropped below the threshold level. otp is ?agged by a low diag pin. the tfa9812 temperature is an i 2 c reading, see section 9.5.9 . under normal conditions thermal foldback prevents the overtemperature protection from being triggered. 8.7.3 overcurrent protection the output current of the power ampli?ers is current-limited. when an output stage exceeds a current of 3 a typical, the output stages are set to 3-state mode and after 1 m s the stages will start operating normally again. these interruptions are not audible. ocp is ?agged by a low diag pin and by a high diag i 2 c status bit, see section 9.5.10 . i 2 c settings remain valid. 8.7.4 overvoltage protection the supply for the power stages (v dda , v ddp ) is protected against overvoltage. when a supply voltage exceeds 20 v the device will enter sleep mode. when the supply voltage has fallen below 20 v again the power-up sequence is started. ovp is ?agged by a low diag pin and by a high diag i 2 c status bit, see section 9.5.10 . i 2 c settings remain valid. 8.7.5 undervoltage protections the supplies are protected against undervoltage. when this is detected the device will enter sleep mode. when the supply voltage has risen to a suf?cient level again the power-up sequence is started. t ab le 20 shows the uvp trigger levels for the v dda and v dda(3v3) supplies:
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 25 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8.7.6 overdissipation protection when the output current of the power ampli?ers exceeds a current value of 3 a and the temperature is above 140 c, overdissipation protection is activated and the device enters sleep mode. a restart will be initiated automatically when the two overdissipation conditions are both changed to false. overdissipation is ?agged by a low diag pin and by a high diag i 2 c status bit, see section 9.5.10 . under normal conditions thermal foldback prevents overdissipation protection from being triggered. i 2 c settings remain valid. 8.7.7 window protection window protection is a feature for protecting the device against shorts from the outputs to the ground or supply lines. if during power-up one of the outputs is shorted to v sspx or v ddp , power-up does not proceed any further. the trigger levels for these conditions are: ? outxx > v dda - 1 v, or ? outxx < refa + 1 v. the wp alarm is ?agged by a low diag pin and by a high diag i 2 c status bit, see section 9.5.10 . 8.7.8 lock protection when the selected clock input source (mclk, bck or crystal) stops running, the tfa9812 is able to detect this and set the output stages to 3-state mode. without this protection peripheral devices in an application might be damaged. the pll lock indication is an i 2 c reading and will be false in the event of a clock interruption, see section 9.5.10 . 8.7.9 underfrequency protection ufp sets the output stages to 3-state mode when the clock input source is too low. the pwm switching frequency can becomes critically low when the clock input source is lower than speci?ed. without ufp peripheral devices in an application might be damaged. the status of the ufp is shown in i 2 c reading register, see section 9.5.10 . 8.7.10 overfrequency protection ofp sets the output stages to 3-state mode when the clock input source is too high. the pwm controller can become unstable when the clock input source is higher than speci?ed. without ofp peripheral devices in an application might be damaged. the status of the ofp is shown in i 2 c reading register, see section 9.5.10 . table 20. undervoltage trigger levels pin name uvp level diag pin (protection active) min max v dda 3 7 v < 8 v low v dda(3v3) 3 1.6 v < 3 v -
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 26 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 8.7.11 invalid bck protection the bck clock signal is veri?ed as being at one of the allowed relative frequencies: 32 f s , 48 f s or 64 f s . if it is not at one of these frequencies the tfa9812 will set the output stages to 3-state mode to prevent audible effects. the mclk clock signal is also veri?ed as being valid, see section 8.2.3 . detection of violation results in an automatic internal overruling of the mclk assignment to bck. 8.7.12 dc blocking the tfa9812 features a high pass ?lter after the i 2 s input to block dc signals. dc values at the output can damage the peripheral devices. the high pass ?lter is always enabled. 8.7.13 overview protections t ab le 21 shows the overview of the protections. table 21. overview protections protections symbol conditions diag pin i 2 c ?ag [1] output recovering tf programmable max. t j > 125 c floating - switching automatic, increasing volume control back to volume setting otp t j > 160 c low diag floating automatic, after 1 m s and t j < 160 c ocp i o > i orm low diag floating automatic, after 1 m s and i o 20 v low diag floating restart (fault to operating when v dda > 8 v and v dda(3v3) >3v) uvp v dda < 8 v or v dda(3v3) <3v low diag floating restart (fault to operating when v dda > 8 v and v dda(3v3) >3v) odp t j > 140 c and i o >i orm low diag floating restart (fault to operating when t j < 140 c or io < i orm ) wp [2] outx > v dda - 1 v or outx < refa + 1 v low diag floating restart (fault to operating when outx < v dda - 1v and outx > v ssa +1v) lp pll out of lock floating lp floating restart (fault to operating when pll is in lock) ufp pll frequency < 45 mhz floating ufp floating restart (fault to operating when pll frequency > 45 mhz)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 27 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] see, section 9.5.10 . [2] window protection is only checked at power-up. 9. i 2 c bus interface and register settings 9.1 i 2 c bus interface the tfa9812 supports the 400 khz i 2 c bus microcontroller interface mode standard. this can be used to control the tfa9812 and to exchange data with it when in i 2 c control mode, see section 8.2.1 . the tfa9812 can operate in i 2 c slave mode only as slave receiver or a slave transmitter. the serial hardware interface involves the pins of the tfa9812 as described in t ab le 22 . voltage values applied to the i 2 c bus device address pins are interpreted as described in t ab le 23 . 9.2 i 2 c bus tfa9812 device addresses t ab le 24 shows the register address options for the tfa9812 as part of the 8-bit byte that contains the device address as well as the bit indicator read/write_not r/!w. the tfa9812 supports four different addresses, each of which can be con?gured using the pins adsel1/plim1 and adsel2/plim2, see t ab le 22 . ofp pll frequency > 140 mhz floating ofp floating restart (fault to operating when pll frequency < 140 mhz) ibp bck/ws is not 32 2, 48 2 or 64 2 floating - floating restart (fault to operating when bck/ws is 32 2, 48 2 or 64 2) table 21. overview protections continued protections symbol conditions diag pin i 2 c ?ag [1] output recovering table 22. i 2 c pins in i 2 c control mode pin name description scl/sfor i 2 c bus clock input sda/ms i 2 c bus data input and output adsel2/plim2 i 2 c bus device address bit a2 adsel1/plim1 i 2 c bus device address bit a1 table 23. i 2 c pin voltages in i 2 c control mode logic value voltage a2/a1 0< v il 1> v ih table 24. i 2 c bus device address (msb) bit (lsb) 11010a2a1 r/!w
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 28 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.3 i 2 c write cycle description t ab le 25 shows the cycle required for writing data to the i 2 c registers of the tfa9812. the byte size is 8 bits. the i 2 c registers of the tfa9812 store two data bytes. data is always written in pairs of two bytes. data transfer is always msb ?rst. the cycle format for writing to the tfa9812 using sda is as follows: 1. the microcontroller asserts a start condition (s). 2. the microcontroller sends the device address (7 bits) of the tfa9812 followed by the r/!w bit set to 0. 3. the tfa9812 asserts an acknowledge (a). 4. the microcontroller writes the 8-bit tfa9812 register address to which the ?rst data byte will be written. 5. the tfa9812 asserts an acknowledge. 6. the microcontroller sends the ?rst byte. this is the most signi?cant byte of the register. 7. the tfa9812 asserts an acknowledge. 8. the microcontroller sends the second byte. 9. the tfa9812 asserts an acknowledgement. 10. the microcontroller can either assert the stop condition (p) or continue with a further pair of data bytes, repeating step 6. in the latter case the targeted register address will have been auto-increased by the tfa9812. 9.4 i 2 c read cycle description t ab le 26 shows the cycle required for reading data from the i 2 c registers of the tfa9812. the byte size is 8 bits. the i 2 c registers of the tfa9812 store two data bytes. data is always read in pairs of two bytes. data transfer is always msb-?rst. the read cycle format for writing to the tfa9812 using sda is as follows: 1. the microcontroller asserts a start condition (s). 2. the microcontroller sends the device address (7 bits) of the tfa9812 followed by the r/!w bit set to 0. 3. the tfa9812 asserts an acknowledge (a). 4. the microcontroller writes the 8-bit tfa9812 register address from which the ?rst data byte will be read. 5. the tfa9812 asserts an acknowledge. 6. the microcontroller asserts a repeated start (sr). 7. the microcontroller resends the device address (7 bits) of the tfa9812 followed by the r/!w bit set to 1. 8. the tfa9812 asserts an acknowledge. table 25. i 2 c write cycle start tfa9812 address r/!w tfa9812 ?rst register address ms databyte ls databyte more data... stop s 11010a 2 a 1 0 a addr a ms1 a ls1 <....> p
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 29 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9. the tfa9812 sends the ?rst byte. this is the most signi?cant byte of the register. 10. the microcontroller asserts an acknowledge. 11. the tfa9812 sends the second byte. 12. the microcontroller asserts either an acknowledge or a negative acknowledge (na). C if the microcontroller has asserted an acknowledge, the targeted register address is auto-increased by the tfa9812 and steps 9 to 12 are repeated. C if the microcontroller has asserted a negative acknowledge, the tfa9812 frees the i 2 c bus and the microcontroller generates a stop condition (p). 9.5 top-level register map t ab le 27 describes the assignments of the various register addresses to the functional control or status areas at top level. there are 47 control registers and 2 status registers. the following subsections give the individual register interpretations and bit level details. table 26. i 2 c read cycle start tfa9812 address r/!w first register address tfa9812 address r/!w ms data byte ls data byte more data... more data... stop s 11010a 2 a 1 0 a addr a sr 11010a 2 a 1 1 a ms1 a ls1 <....> na p table 27. top-level register map register address (hex) default (hex) access see: description 0x00 0x0020; legacy_mode r/w section 9.5.1 interpolator settings and soft mute 0x0021; i 2 c_mode 0x01 0x0000 r/w section 9.5.2 volume control 0x02 0x0006 r/w section 9.5.3 format digital in 0x03 0x0002 r/w section 9.5.4 equalizer con?guration 0x04 0x0058 r/w section 9.5.5 equalizer_a1 word_1; word_1 for equalizer band a1, see section 8.5.1.2 0x05 0x4f40 r/w section 9.5.5 equalizer_a1 word_2; see section 8.5.1.2 0x06 0x0058 r/w section 9.5.5 equalizer_b1 word_1 0x07 0x4f40 r/w section 9.5.5 equalizer_b1 word_2 0x08 0x0a63 r/w section 9.5.5 equalizer_c1 word_1 0x09 0x4240 r/w section 9.5.5 equalizer_c1 word_2 0x0a 0x0a63 r/w section 9.5.5 equalizer_d1 word_1 0x0b 0x4240 r/w section 9.5.5 equalizer_d1 word_2 0x0c 0x00b7 r/w section 9.5.5 equalizer_a2 word_1 0x0d 0x4e40 r/w section 9.5.5 equalizer_a2 word_2 0x0e 0x00b7 r/w section 9.5.5 equalizer_b2 word_1 0x0f 0x4e40 r/w section 9.5.5 equalizer_b2 word_2 0x10 0x14a2 r/w section 9.5.5 equalizer_c2 word_1
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 30 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input reserved registers or bits will be indicated by rsd. 0x11 0x7a40 r/w section 9.5.5 equalizer_c2 word_2 0x12 0x14a2 r/w section 9.5.5 equalizer_d2 word_1 0x13 0x7a40 r/w section 9.5.5 equalizer_d2 word_2 0x14 0x0156 r/w section 9.5.5 equalizer_a3 word_1 0x15 0x4d40 r/w section 9.5.5 equalizer_a3 word_2 0x16 0x0156 r/w section 9.5.5 equalizer_b3 word_1 0x17 0x4d40 r/w section 9.5.5 equalizer_b3 word_2 0x18 0x2871 r/w section 9.5.5 equalizer_c3 word_1 0x19 0x7140 r/w section 9.5.5 equalizer_c3 word_2 0x1a 0x2871 r/w section 9.5.5 equalizer_d3 word_1 0x1b 0x7140 r/w section 9.5.5 equalizer_d3 word_2 0x1c 0x02a5 r/w section 9.5.5 equalizer_a4 word_1 0x1d 0x4c40 r/w section 9.5.5 equalizer_a4 word_2 0x1e 0x02a5 r/w section 9.5.5 equalizer_b4 word_1 0x1f 0x4c40 r/w section 9.5.5 equalizer_b4 word_2 0x20 0x4a80 r/w section 9.5.5 equalizer_c4 word_1 0x21 0x5040 r/w section 9.5.5 equalizer_c4 word_2 0x22 0x4a80 r/w section 9.5.5 equalizer_d4 word_1 0x23 0x5040 r/w section 9.5.5 equalizer_d4 word_2 0x24 0x0534 r/w section 9.5.5 equalizer_a5 word_1 0x25 0x4b40 r/w section 9.5.5 equalizer_a5 word_2 0x26 0x0534 r/w section 9.5.5 equalizer_b5 word_1 0x27 0x4b40 r/w section 9.5.5 equalizer_b5 word_2 0x28 0xd961 r/w section 9.5.5 equalizer_c5 word_1 0x29 0x4840 r/w section 9.5.5 equalizer_c5 word_2 0x2a 0xd961 r/w section 9.5.5 equalizer_d5 word_1 0x2b 0x4840 r/w section 9.5.5 equalizer_d5 word_2 0x2c 0x0005 r/w section 9.5.6 pwm signal control 0x2d 0x000e r/w section 9.5.7 digital-in clock con?guration 0x2e 0x0000 r/w section 9.5.8 thermal foldback control 0x2f - r section 9.5.9 tfa9812 temperature 0x30 - r section 9.5.10 miscellaneous status table 27. top-level register map continued register address (hex) default (hex) access see: description
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 31 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.1 interpolator settings and soft mute 9.5.2 volume control table 28. register address 00h: miscellaneous i 2 c interpolator settings bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default 00000000 bit 7 6 5 4 3 2 1 0 symbol rsd inv_pol roff1 roff0 fdemp2 fdemp1 fdemp0 s_mute default 00100001/0 table 29. bit description of register 00h: miscellaneous i 2 c interpolator settings bit symbol description 6 inv_pol enable polarity inversion: 0 = no polarity inversion (left audio signal connected to channel 1; right signal to channel 2) 1 = polarity inversion enabled 5 to 4 roff[1:0] filter roll-off sharpness: 0 = slow ?lter roll-off (2 to 8 f s ) 3 stop band > 0.7619 f s 1 = slow ?lter roll-off (2 to 8 f s ) 3 stop band > 0.7619 f s 2 = fast ?lter roll-off (2 to 8 f s ) 3 stop band > 0.6094 f s 3 = fast ?lter roll-off (2 to 8 f s ) 3 stop band > 0.6094 f s 3 to 1 fdemp[2:0] digital de-emphasis setting: 0 = no digital de-emphasis 1 = digital de-emphasis for f s = 32 khz 2 = digital de-emphasis for f s = 44.1 khz 3 = digital de-emphasis for f s = 48 khz 4 = digital de-emphasis for f s = 96 khz 5 to 8 = no digital de-emphasis 0 s_mute soft mute: 0 = soft mute disabled using raised cosine (default in legacy control mode) 1 = soft mute enabled using raised cosine (default in i 2 c control mode) table 30. register address 01h: volume control bit 15 14 13 12 11 10 9 8 symbol vol_l7 vol_l6 vol_l5 vol_l4 vol_l3 vol_l2 vol_l1 vol_l0 default 00000000 bit 7 6 5 4 3 2 1 0 symbol vol_r7 vol_r6 vol_r5 vol_r4 vol_r3 vol_r2 vol_r1 vol_r0 default 00000000
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 32 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.3 digital input format 9.5.4 equalizer con?guration table 31. bit description of register 00h: miscellaneous i 2 c interpolator settings bit symbol description 15 to 8 vol_l[15:8] see t ab le 16 for suppression levels on left channel as function of data byte setting. 7 to 0 vol_r[7:0] see t ab le 16 for suppression levels on right channel as function of data byte setting. table 32. register address 02h: digital input format bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default 00000000 bit 7 6 5 4 3 2 1 0 symbol rsd rsd rsd rsd di_for2 di_for1 di_for0 ws_pol default 00000110 table 33. bit description of register 02h: digital input format bit symbol description 3 to 1 di_for[2:0] digital audio input format: 0 = rsd 1 = rsd 2 = msb-justi?ed data up to 24 bits 3 = i 2 s data up to 24 bits 4 = lsb-justi?ed 16-bit data 5 = lsb-justi?ed 18-bit data 6 = lsb-justi?ed 20-bit data 7 = lsb-justi?ed 24-bit data 0 ws_pol enable ws signal polarity inversion: 0 = no ws signal polarity inversion 1 = ws signal polarity inversion enabled table 34. register address 03h: equalizer con?guration bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default 00000000 bit 7 6 5 4 3 2 1 0 symbol rsd rsd rsd rsd rsd rsd eq_bp eq_bnd default 00000010
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 33 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.5 equalizer settings [1] default settings are shown in t ab le 27 . the corresponding equalizer con?guration is shown in t ab le 40 . [1] default settings are shown in t ab le 27 . the corresponding equalizer con?guration is shown in t ab le 40 . table 35. bit description of register 03h: equalizer con?guration bit symbol description 1 eq_bp equalizer bypass enable: 0 = equalizer not bypassed 1 = equalizer bypassed 0 eq_bnd equalizer 10-band or 5-band con?guration selection: 0 = 10-band equalizer con?guration enabled 1 = 5-band equalizer con?guration enabled table 36. register addresses xxh = 04, 06...2a for word1 for equalizer 'yy' see figure 9 bit 15 14 13 12 11 10 9 8 symbol eyy_t 1 eyy_k 1m 10 eyy_k 1m 9 eyy_k 1m 8 eyy_k 1m 7 eyy_k 1m 6 eyy_k 1m 5 eyy_k 1m 4 default [1] -------- bit 7 6 5 4 3 2 1 0 symbol eyy_k 1m 3 eyy_k 1m 2 eyy_k 1m 1 eyy_k 1m 0 eyy_k 1e 3 eyy_k 1e 2 eyy_k 1e 1 eyy_k 1e 0 default [1] -------- table 37. register addresses xxh = 05, 07...2b for word2 for equalizer 'yy' see figure 9 bit 15 14 13 12 11 10 9 8 symbol eyy_t 2 eyy_k 2m 3 eyy_k 2m 2 eyy_k 2m 1 eyy_k 2m 0 eyy_k 2e 2 eyy_k 2e 1 eyy_k 2e 0 default -------- bit 7 6 5 4 3 2 1 0 symbol eyy_k 0 6 eyy_k 0 5 eyy_k 0 4 eyy_k 0 3 eyy_k 0 2 eyy_k 0 1 eyy_k 0 0 eyy_s default --------
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 34 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input fig 9. equalizer con?guration and register location mapping left in left out 2 5 or 2 10 right in right out 2 5 or 2 10 a1 c1 b1 d1 d2 d3 d4 d5 b2 b3 b4 b5 c2 c3 c4 c5 a2 a3 a4 a5 010aaa404 table 38. bit description of registers xxh = 04, 06...2a bit symbol description 15 eyy_t 1 the ?lter con?guration bit t 1, see section 8.5.1.2 . 14 to 4 eyy_k1 m [10:0] the 11 mantissa bits of the ?lter parameter k 1, see section 8.5.1.2 . 3 to 0 eyy_k1 e [3:0] the four exponent bits of the ?lter parameter k 1 , see section 8.5.1.2 . table 39. bit description of registers xxh = 05, 07...2b bit symbol description 15 eyy_t 2 the ?lter con?guration bit t 2 , see section 8.5.1.2 . 14 to 11 eyy_k 2m [3:0] the four mantissa bits of the ?lter parameter k 2 , see section 8.5.1.2 . 10 to 8 eyy_k 2e [2:0] the three exponent bits of the ?lter parameter k 2 , see section 8.5.1.2 . 7 to 1 eyy_k 0 [6:0] the seven bits of the ?lter gain parameter k 0 , see section 8.5.1.2 . 0 eyy_s the ?lter scale-factor bits, see section 8.5.1.2 : 0 = no scaling applied 1 = - 6 db ampli?cation enabled
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 35 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.6 pwm signal control table 40. default con?guration equalizer for f s = 44.1 khz band a1/b1 a2/b2 a3/b3 a4/b4 a5/b5 c1/d1 c2/d2 c3/d3 c4/d4 c5/d5 frequency (hz) 31 63 125 250 500 1000 2000 4000 8000 16000 q-factor 1111111111 gain (db) 0000000000 table 41. register 2ch: pwm signal control bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default 00000000 bit 7 6 5 4 3 2 1 0 symbol rsd plim1 plim0 pw_off pw_sf1 pw_sf0 pw_cl1 pw_cl0 default 00000101 table 42. bit description address 2ch bit symbol description 7 gain +24 db gain boost: 0 = gain boost 0 db 1 = gain boost +24 db 6 to 5 plim[1:0] output power limitation: 0 = maximum power 1 = maximum power - 1.5 db 2 = maximum power - 3.0 db 3 = maximum power - 4.5 db 4 pw_off hard mute control: 0 = no hard mute 1 = hard mute enabled, implemented by pwm signal with 50 % duty cycle 3 to 2 pw_sf[1:0] pwm switching frequency: 0 = 350 khz 1 = 400 khz 2 = 700 khz 3 = 750 khz 1 to 0 pw_cl[1:0] pwm clip level: 0 = < 0.5 % thd 1 = 10 % thd 2 = 20 % thd 3 = 30 % thd
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 36 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.7 digital-in clock con?guration 9.5.8 thermal foldback control table 43. register 2dh: digital-in clock con?guration bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default 00000000 bit 7 6 5 4 3 2 1 0 symbol rsd rsd rsd fsub3 fsub2 fsub1 fsub0 di_ms default 00001110 table 44. bit description of register 2dh:digital-in clock con?guration bit symbol description 4 to 1 fsub[3:0] sample frequency f s of digital-in signal: 0 = 8 khz 1 = 11.025 khz 2 = 12 khz 3 = 16 khz 4 = 22.05 khz 5 = 24 khz 6 = 32 khz 7 = 44.1 khz 8 = 48 khz 9 = 64 khz 10 = 88.2 khz 11 = 96 khz 12 = 128 khz 13 = 176.4 khz 14 = 192 khz 15 = rsd 0 di_ms tfa9812 digital-in master/slave mode selection: 0 = slave mode 1 = master mode table 45. register 2eh: thermal foldback control bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd tp_thr9 tp_thr8 default 00000000 bit 7 6 5 4 3 2 1 0 symbol tp_thr7 tp_thr6 tp_thr5 tp_thr4 tp_thr3 tp_thr2 tp_thr1 tp_thr0 default 00000000
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 37 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 9.5.9 tfa9812 temperature 9.5.10 miscellaneous status table 46. bit description of register 2dh: digital-in clock con?guration bit symbol description 9 to 0 tp_thr[9:0] reduction on the maximum temperature of 125 c. the reduction can be calculated by: reduction integer (tp_thr[9:0] 2.4552 ----------------------------------- in c = table 47. register 2fh: tfa9812 temperature bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd temp9 temp8 default -------- bit 7 6 5 4 3 2 1 0 symbol temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 default -------- table 48. bit description of register 2dh: digital-in clock con?guration bit symbol description 9 to 0 temp[9:0] temperature of the tfa9812, which can be calculated in c using: temp tfa9812 = (1023 - temp[9:0]) / 2.4552 table 49. register 30h: miscellaneous status bit 15 14 13 12 11 10 9 8 symbol rsd rsd rsd rsd rsd rsd rsd rsd default -------- bit 7 6 5 4 3 2 1 0 symbol rsd ofp ufp uvp1v8 uvp3v3 diag lp mute default -------- table 50. bit description of register 30h: miscellaneous status bit symbol description 6 ofp pll frequency-over-range indicator: 0 = pll frequency in supported range 1 = pll frequency exceeds highest supported frequency value 5 ufp pll frequency under-range indicator: 0 = pll frequency in supported range 1 = pll frequency below lowest supported frequency value 4 uvp1v8 undervoltage detector for pins 4 and 41: 0 = no uvp has been detected 1 = a uvp has been detected since the last read-out of the register
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 38 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] the diagnostic pin 30 diag is ?agged when several protection mechanisms have been active, see section 8.7 . 9.6 overview of functional control in each control mode t ab le 51 shows the control level supported by either i 2 c or legacy control mode for all functions described in section 9 . it summarizes the information provided in the detailed description of each function. 3 uvp3v3 undervoltage detector for pins 3 and 40: 0 = no uvp has been detected 1 = a uvp has been detected since the last read-out of the register 2 diag diagnostic pin ?agging status [1] : 0 = diagnostic pin has not been ?agged low 1 = diagnostic pin has been ?agged low since the last read-out of the register 1 lp pll lock protection indicator: 0 = pll is in locked status 1 = pll is not in locked status 0 mute soft mute status: 0 = no soft-mute or soft mute/demute in progress 1 = audio signal muted as result of a soft mute table 50. bit description of register 30h: miscellaneous status continued bit symbol description table 51. functional control support in i 2 c and legacy control modes d = ?xed control setting, determined by default i 2 c register setting; n = not supported; y = fully supported (i.e. all options implemented in the tfa9812). control function reference i 2 c mode legacy mode i 2 c register content section 9 y n/d sleep mode enable section 8.2.2 yy operating mode enable section 8.2.2 yy 3-state mode enable section 8.2.2 yy master/slave i 2 s section 8.2.3 yy mclk/bck master input clock selection section 8.2.3 auto auto digital audio input format selection section 8.4 y subset selection f s = 8 khz to192 khz section 8.4.1 yd [1] equalizer enable and con?guration section 8.5.1 yd [2] detailed equalizer settings section 8.5.1 yn digital volume control per channel section 8.5.2 yn analog volume control (shared for two channels) section 8.5.3 ny de-emphasis for subset of allowed f s section 8.5.3 yn soft mute section 8.5.3 yy [3] hard mute section 8.5.3 yn polarity switch enable section 8.5.4 yn +24 db gain boost section 8.5.6 yy
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 39 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] 32 khz, 44.1 khz and 48 khz supported [2] bypass. [3] special legacy mode implementation. [4] 10 % clip level. [5] 400 khz. 10. internal circuitry clip level control section 8.5.5 yd [4] output power limit level control section 8.5.6 yy pwm signal frequency selection section 8.5.7 yd [5] thermal foldback threshold temperature control section 8.7.1 yn table 51. functional control support in i 2 c and legacy control modes continued d = ?xed control setting, determined by default i 2 c register setting; n = not supported; y = fully supported (i.e. all options implemented in the tfa9812). control function reference i 2 c mode legacy mode table 52. internal circuitry pin symbol equivalent circuitry 1 xtalin 32 avol 2 xtalout 3v dda(3v3) 40 v ddd(3v3) 1, 32 esd v ss1 , v ss2 , refa, refd exposed die paddle 010aaa459 staba 2 v ss1 , v ss2 , refa, refd, exposed die-paddle 010aaa460 esd v ss1 , v ss2 , refa, refd, exposed die-paddle 010aaa461 3, 40 esd
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 40 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 4 staba 41 stabd 5 refa 6v dda 7 test1 9 stab2 28 stab1 10/11 v ssp2 18/19 v ddp 26/27 v ssp1 12 boot2n 15 boot1p 22 boot2p 25 boot1n table 52. internal circuitry continued pin symbol equivalent circuitry v dda(3v3), v ddd(3v3) 010aaa462 4, 41 v ss1 , v ss2 , refa, refd, exposed die-paddle esd 010aaa463 24 v v ss1 , refd, v ss2 , exposed die-paddle 6 5 010aaa464 7 v dda 13 k w v ss1 v dda 010aaa465 9, 28 12 v v ss1 010aaa466 24 v 18/19 10/11, 26/27 010aaa467 12 v 12, 15, 22, 25 out2n, out1p, out2p, out1n
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 41 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 13/14 out2n 16/17 out1p 20/21 out2p 23/24 out1n 29 diag 30 cdelay 31 powerup 33 enable 34 gain 35 csel 36 adsel2/plim2 37 adsel1/plim1 43 test2 table 52. internal circuitry continued pin symbol equivalent circuitry 010aaa468 v ddp 13/14, 16/17, 20/21, 23/24 v ssp1 , v ssp2 010aaa469 v dda v ss1 v ss1 29 010aaa470 200 na 5 k w 2 m a v dda 30 discharge v ss1 010aaa471 31 v dda 3 k w 250 na v ss1 010aaa472 v ss1 , v ss2 , refa, refd, exposed die-paddle 33, 34, 35, 36, 37, 43 pull-down 50 m a esd
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 42 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 11. limiting values 38 scl/sfor 39 sda/ms 45 ws 46 bck 47 mclk table 52. internal circuitry continued pin symbol equivalent circuitry 010aaa473 v ss1 , v ss2 , refa, refd, exposed die-paddle 38, 44 esd 010aaa474 v ss1 , v ss2 , refa, refd, exposed die-paddle 39 esd 010aaa475 vss1, vss2, refa, refd, exposed die-paddle esd 45, 46, 47 v ddd(3v3) table 53. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage - v ss [1] - 0.3 +24 v v ddp power supply voltage - v sspx ; x = 1.2 - 0.3 +24 v v dda(3v3) analog supply voltage (3.3 v) - v ss [1] - 0.3 +4.6 v v ddd(3v3) digital supply voltage (3.3 v) - v ss [1] - 0.3 +4.6 v t j junction temperature - 150 c t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c p power dissipation 5 w
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 43 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] v ss = v ss1 = v ss2 = refa = refd 12. thermal characteristics [1] measured in a jedec high k-factor test board (standard eia/jesd 51-7). [2] measured in free air with natural convection. [3] strongly depends on where measurement is made on the case: worst-case value stated. v x voltage on pin x diag [1] v ss - 0.3 v ss + 12 v powerup [1] v ss - 0.3 v dda + 0.3 v enable, gain, csel, adsel2/plim2, adsel2/plim1, scl/sfor, sda/ms, data, ws, bck, mclk [1] v ss - 0.5 v ss + 5.5 v avol [1] v ss - 0.5 v ss + 4.6 v v esd electrostatic discharge voltage according to the human body model stab1 and stab2 with respect to other pins - 1750 +1750 v all other pins - 2+2 kv according to the charge device model - 500 +500 v table 53. limiting values continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 54. thermal characteristics symbol parameter condition min typ max unit r th(j-a) thermal resistance from junction to ambient no air ?ow, jedec board [1] [2] - - 42 k/w no air ?ow; typical 4l board in the nxp 4l reference application [2] - - 36 k/w no air ?ow; typical 2l board in the nxp 2l reference application [2] - - 42 k/w r th(j-c) thermal resistance from junction to case [3] 5 - - k/w r th(j-lead) thermal resistance from junction to lead worst-case pin 5 - - k/w
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 44 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 13. characteristics 13.1 dc characteristics table 55. dc characteristics unless speci?ed otherwise, v dda =v ddp = 12 v, v ssp1 = v ssp2 = 0 v, v dda(3v3) =v ddd(3v3) = 3.3 v, v ss1 =v ss2 = refd = refa = 0 v, t amb =25 c, r l =8 w , f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter condition min typ max unit supply voltage v dda analog supply voltage 81220v v ddp power supply voltage 8 12 20 v v dda(3v3) analog supply voltage (3.3 v) 3.0 3.3 3.6 v v ddd(3v3) digital supply voltage (3.3 v) 3.0 3.3 3.6 v i p supply current soft mute mode, with load, ?lter and snubbers connected [1] -3845ma sleep mode [1] - 160 270 m a i dda(3v3) analog supply current (3.3 v) operating mode i 2 s slave mode - 2 4 ma i 2 s master mode - 4 6 ma sleep mode v dda =v ddp =12v - 120 - m a v dda =v ddp =1v - 40 70 m a i ddd(3v3) digital supply current (3.3 v) operating mode i 2 s slave mode - 15 25 ma i 2 s master mode - 25 40 ma sleep mode; data=ws=bck= mlck = 0 v -430 m a ampli?er output pins; pins out1p, out1n, out2p and out2n | v o(offset) | output offset voltage soft mute mode - - 5 mv power-up pin v ih high-level input voltage with respect to v ss1 2.1 - v ddd(3v3) v v il low-level input voltage with respect to v ss1 - 0.3 - +0.8 v i i input current - 0.1 20 m a mclk, bck, ws, data pin v ih high-level input voltage with respect to v ss2 0.7 v ddd(3v3) -- v v il low-level input voltage with respect to v ss2 - - 0.3 v ddd(3v3) v c i input capacitance - - 3 pf
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 45 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input v oh high-level output voltage at i oh = - 0.4 ma v ddd(3v3) - 0.4 v - - v v ol low-level output voltage at i ol = 4 ma - - 400 mv c l load capacitance - - 50 pf sda/ms, scl/sfor pin v ih high-level input voltage with respect to v ss2 0.7 v ddd(3v3) - 5.5 v v il low-level input voltage with respect to v ss2 - 0.3 - 0.3 v ddd(3v3) v v hys(i) input hysteresis voltage with respect to v ss2 0.1 v ddd(3v3) -- v c i input capacitance - - 2.5 pf v ol low-level output voltage at i ol = 3 ma - - 400 mv enable, gain, csel, adsel2/plim2, asel1/plim1 pin v ih high-level input voltage with respect to v ss2 0.7 v ddd(3v3) -- v v il low-level input voltage with respect to v ss2 - 0.3 v ddd(3v3) v v hys(i) input hysteresis voltage with respect to v ss2 0.1 v ddd(3v3) -- v i i input current - 50 93 m a regulators v o output voltage stab1 - v ss1 10 11 12 v stab2 - v ss1 10 11 12 v staba - refa 1.65 1.8 1.95 v stabd - refd 1.65 1.8 1.95 v cdelay pin v cdelay voltage on pin cdelay relative to positive analog power supply -v dda - 1- v crystal pins v o(xtal)(p-p) peak-to-peak crystal oscillator output voltage with respect to v ss2 - 1.8 - v avol pin v i input voltage mute level, with respect to v ss2 0.77 0.8 0.83 v 0 db level with respect to v ss2 2.74 2.8 2.86 v i i input current - - 1 m a table 55. dc characteristics continued unless speci?ed otherwise, v dda =v ddp = 12 v, v ssp1 = v ssp2 = 0 v, v dda(3v3) =v ddd(3v3) = 3.3 v, v ss1 =v ss2 = refd = refa = 0 v, t amb =25 c, r l =8 w , f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter condition min typ max unit
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 46 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] i p is the current through the analog supply voltage (v dda ) pin added to the current through the power supply voltage (v ddp ) pin. [2] thermal foldback temperature sensor is not located at hottest spot. hottest spot is 12 c higher. [3] current limiting concept: in overcurrent condition no interruption of the audio signal in case of impedance drop. [4] pll output frequency not external available. thermal foldback (tf) t act(th_fold) thermal foldback activation temperature [2] 118 125 132 c overtemperature protection (otp) t act(th_prot) thermal protection activation temperature - - 160 c overvoltage protection (ovp) v p(ovp) overvoltage protection supply voltage 20 22.3 24 v undervoltage protections (uvp) v p(uvp) undervoltage protection supply voltage uvp on v dda 7 7.5 8 v uvp on v dda(3v3) 1.6 2.2 3.0 v overcurrent protection (ocp) i o(ocp) overcurrent protection output current [3] 3.0 3.3 3.6 a window protection (wp) v o output voltage high level - v dda - 1- v low level - refa + 1 - v overfrequency protection (ofp) f ofp overfrequency protection frequency at pll output frequency [4] 100 140 185 mhz underfrequency protection (ofp) f ufp underfrequency protection frequency at pll output frequency [4] 30 45 60 mhz table 55. dc characteristics continued unless speci?ed otherwise, v dda =v ddp = 12 v, v ssp1 = v ssp2 = 0 v, v dda(3v3) =v ddd(3v3) = 3.3 v, v ss1 =v ss2 = refd = refa = 0 v, t amb =25 c, r l =8 w , f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter condition min typ max unit
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 47 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 13.2 ac characteristics table 56. ac characteristics unless speci?ed otherwise, v dda =v ddp = 12 v, v dda(3v3) =v ddd(3v3) = 3.3 v, t amb =25 c, r s < 0.1 w [1] , r l =8 w , f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter condition min. typ. max. unit output power per channel p o(rms) rms output power continuous time output power per channel; thd = 1 %, r l = 6 w v dda = v ddp = 12 v - 7.9 - w v dda = v ddp = 15 v - 12 - w continuous time output power per channel; thd = 10 %, r l = 6 w v dda = v ddp = 12 v - 9.7 - w short time ( 10 s) output power per channel; thd = 10 %, r l = 6 w v dda = v ddp = 15 v - 15 - w continuous time output power per channel; thd = 1 %, r l = 8 w v dda = v ddp = 12 v - 6.6 - w v dda = v ddp = 15 v - 10 - w continuous time output power per channel; thd = 10 %, r l = 8 w v dda = v ddp = 12 v - 8.3 - w v dda = v ddp = 13.5 v - 10 - w v dda = v ddp = 15 v - 12 - w short time ( 10 s) output power per channel; thd = 10 %, r l = 8 w v dda = v ddp = 17 v - 15 - w performance thd+n total harmonic distortion-plus-noise p o = 1 w; aes17 brick wall ?lter - 0.07 0.1 % s/n signal-to-noise ratio v o = 10 v; a-weighted - 103 - db v n(o) output noise voltage mclk clock jitter < 200 ps; aes17 brick-wall ?lter operating mode - 70 - m v soft mute mode - 70 - m v hard mute mode - 30 - m v a cs channel separation p o(rms) = 1 w; aggressor channel: f i = 1 khz 50 54 - db svrr supply voltage ripple rejection v ripple = 2 v pp ; f ripple = 100 hz 55 60 - db h po output power ef?ciency r l = 8 w ; p o(rms) = 8.3 w [2] -88- % r l = 6 w ; p o(rms) = 9.7 w [2] -83- % power-up times and delay times t d(on) turn-on delay time - - 155 ms
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 48 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] r s is the series resistance of inductor of low-pass lc ?lter in the application. [2] output power measured across the loudspeaker load. this is based on indirect measurement of r dson . 13.3 timing t pd propagation delay f s = 8 khz - 3.6 - ms 11.025 khz - 2.58 - ms 12 khz - 2.39 - ms 16 khz - 1.78 - ms 22.05 khz - 1.3 - ms 24 khz - 1.18 - ms 32 khz - 892 - m s 44.1 khz - 664 - m s 48 khz - 600 - m s 64 khz - 458 - m s 88.2 khz - 320 - m s 96 khz - 306 - m s 128 khz - 67.2 - m s 176.4 khz - 48 - m s 192 khz - 40.8 - m s pwm output t r rise time i o = 0 a - 10 - ns t f fall time i o = 0 a - 10 - ns t w(min) minimum pulse width i o = 0 a - 40 - ns r dson drain-source on-state resistance per output mosfet, for low and high side - 0.28 0.35 w d max maximum duty factor - - 0.96 - table 56. ac characteristics continued unless speci?ed otherwise, v dda =v ddp = 12 v, v dda(3v3) =v ddd(3v3) = 3.3 v, t amb =25 c, r s < 0.1 w [1] , r l =8 w , f i = 1 khz, f s = 44.1 khz, f sw = 400 khz, 24-bit i 2 s input data, mclk clock mode, typical application diagram ( figure 13 ). symbol parameter condition min. typ. max. unit table 57. characteristics i 2 c bus interface; see figure 10 v ddd(3v3) =v dda(3v3) = 2.7 v to 3.6 v; v dda =v ddp = 8 v to 20 v;t amb = - 20 c to +85 c; all voltages referenced to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - m s t high high period of the scl clock 0.6 - - m s t r rise time sda and scl signals [1] 20 + 0.1 c b -- ns t f fall time sda and scl signals [1] 20 + 0.1 c b -- ns t hd;sta hold time (repeated) start condition [2] 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 49 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input [1] c b is the total capacitance of one bus line in pf. the maximum capacitive load for each bus line is 400 pf. [2] after this period, the ?rst clock pulse is generated. [3] to be suppressed by the input ?lter. 14. application information 14.1 output power estimation the output power just before clipping can be estimated using equation 10 : (10) where: v p = supply voltage (v) (v ddp -v ssp ). r l = load impedance ( w ). r dson = on resistance power switch ( w ). r s = series resistance output inductor ( w ). t su;sto set-up time for stop condition 0.6 - - m s t buf bus free time between a stop and start condition 1.3 - - m s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - m s t sp pulse width of spikes that must be suppressed by the input ?lter [3] 0 - 50 ns c b capacitive load for each bus line - - 400 pf table 57. characteristics i 2 c bus interface; see figure 10 continued v ddd(3v3) =v dda(3v3) = 2.7 v to 3.6 v; v dda =v ddp = 8 v to 20 v;t amb = - 20 c to +85 c; all voltages referenced to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit fig 10. timing t buf t low t r t f t hd;sta t su;sta t hd;dat t high t su;dat t hd;sta t su;sto t sp p s sr p sda scl 010aaa225 p o (0.5%) r l r l 2r dson r s + () + ---------------------------------------------------- ? ?? d max v p ? ?? 2 2r l --------------------------------------------------------------------------------------------- - =
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 50 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input d max = maximum duty factor (0.96). the output power at 10 % thd can be estimated using equation 11 : (11) figure 11 and figure 12 show the estimated output power at thd = 0.5 % and thd = 10 % as a function of btl supply voltage for different load impedances. 14.2 output current limiting the peak output current is internally limited above a level o f 3 a minimum. during normal operation the output current should not exceed this threshold level of 3 a otherwise the output signal will be distorted. the peak output current in btl can be estimated using equation 12 : (12) where: v p = supply voltage (v) (v ddp -v ssp ) r l = load impedance ( w ) r dson = 'on' resistance power switch ( w ) r s = series resistance output inductor ( w ) p o (10%) 1.25 p o (0.5%) = (1) 6 w (2) 8 w (3) 16 w (1) 6 w (2) 8 w (3) 16 w fig 11. btl p o (0.5 %) as a function of v p fig 12. btl p o (10 %) as a function of v p v p (v) 824 20 12 16 010aaa347 10 20 30 0 (1) (2) (3) p o (0.5 %) (w/channel) v p (v) 824 20 12 16 010aaa348 15 30 45 0 (1) (2) (3) p o (10 %) w/channel i o max () v p r l 2 + r dson r s + ? -----------------------------------------------------
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 51 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input remark: a 4.8 w speaker (6 w speaker with 20 % spread) in btl con?guration can be used up to a supply voltage of 17 v without running into current limiting. current limiting (clipping) will avoid audio holes, but it causes a distortion comparable to voltage clipping. 14.3 speaker con?guration and impedance for a ?at-frequency response (second-order butterworth ?lter) it is necessary to change the low pass ?lter components l lc and c lc according to the speaker con?guration and impedance. 14.4 typical application schematics table 58. filter component values impedance ( w ) l lc ( m h) c lc (nf) 6 15 680 8 18 560 16 47 330
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 52 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14.4.1 i 2 s slave mode and legacy control mode fig 13. simpli?ed application diagram for i 2 s slave mode and legacy control mode tfa9812 adsel1/plim1 out1n out1n boot2p out2p out2p v ddp v ddp out1p out1p boot1p out2n out2n adsel2/plim2 xtalin xtalout v dda(3v3) staba refa v dda test1 v ss1 stab2 v ssp2 v ssp2 boot2n csel 24 db gain enable avol powerup cdelay diag stab1 v ssp1 v ssp1 boot1n scl/sfor sda/ms v ddd(3v3) stabd refd test2 data ws bck mclk v ss2 exposed die paddle 36 37 38 39 40 41 42 43 44 45 46 47 48 35 34 33 32 31 30 29 28 27 26 25 enable dc-volume control powerup diagnostic c delay 1 nf c stab 100 nf i 2 s data i 2 s ws i 2 s bck i 2 s mlck (optional) v ddd c vddd 100 nf c stabd 1 m f c vdda 100 nf 3.3 v vpa c stab 100 nf c vpa 100 nf c stab 100 nf 12 3 4 56 789 101112 010aaa476 c boot 15 nf c sn 470 pf c sn 470 pf c lc 680 nf c lc 680 nf c boot 15 nf r sn 10 w r sn 10 w c lc 680 nf c lc 680 nf lic s2 f2 s1 f1 15 m h 24 23 22 21 20 19 18 17 16 15 14 13 c vddp c vddp vp out1 + - 6 w to 8 w out2 + - 6 w to 8 w c boot 15 nf c boot 15 nf f2 s2 f1 s1 15 m h lic r sn 10 w r sn 10 w c sn 470 pf c sn 470 pf power in v p = 8 v to 20 v gnd c vddp 220 m f / 25 v r vdda 10 w vpa vp 100 nf 100 nf r staba 1 k w
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 53 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14.4.2 i 2 s slave mode and i 2 c control mode fig 14. simpli?ed application diagram for i 2 s slave mode and i 2 c control mode tfa9812 adsel1/plim1 out1n out1n boot2p out2p out2p v ddp v ddp out1p out1p boot1p out2n out2n adsel2/plim2 xtalin xtalout v dda(3v3) staba refa v dda test1 v ss1 stab2 v ssp2 v ssp2 boot2n csel gain enable avol powerup cdelay diag stab1 v ssp1 v ssp1 boot1n scl/sfor sda/ms v ddd(3v3) stabd refd test2 data ws bck mclk v ss2 exposed die paddle 36 37 38 39 40 41 42 43 44 45 46 47 48 35 34 33 32 31 30 29 28 27 26 25 enable powerup diagnostic c delay 1 nf c stab 100 nf i 2 c scl i 2 c sda i 2 s data i 2 s ws i 2 s bck i 2 s mlck vddd c vddd 100 nf c stabd 1 m f c vdda 100 nf 3.3 v vpa c stab 100 nf c vpa 100 nf c stab 100 nf 1 2 3 4 5 6 7 8 9 10 11 12 010aaa477 c boot 15 nf c sn 470 pf c sn 470 pf c lc 680 nf c lc 680 nf c boot 15 nf r sn 10 w r sn 10 w c lc 680 nf c lc 680 nf lic s2 f2 s1 f1 15 m h 24 23 22 21 20 19 18 17 16 15 14 13 c vddp c vddp vp out1 + - 6 w to 8 w out2 + - 6 w to 8 w c boot 15 nf c boot 15 nf f2 s2 f1 s1 15 m h lic r sn 10 w r sn 10 w c sn 470 pf c sn 470 pf 3.3 v power in v p = 8 v to 20 v gnd c vddp 220 m f / 25 v r vdda 10 w vpa vp 100 nf 100 nf r staba 1 k w
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 54 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14.4.3 i 2 s master mode and legacy control mode fig 15. simpli?ed application diagram for i 2 s master mode and legacy control mode tfa9812 adsel1/plim1 out1n out1n boot2p out2p out2p v ddp v ddp out1p out1p boot1p out2n out2n adsel2/plim2 xtalin xtalout v dda(3v3) staba refa v dda test1 v ss1 stab2 v ssp2 v ssp2 boot2n csel 24 db gain enable avol powerup cdelay diag stab1 v ssp1 v ssp1 boot1n scl/sfor sda/ms v ddd(3v3) stabd refd test2 data ws bck mclk v ss2 exposed die paddle 36 37 38 39 40 41 42 43 44 45 46 47 48 35 34 33 32 31 30 29 28 27 26 25 enable dc-volume control powerup diagnostic c delay 1 nf c stab 100 nf i 2 s data i 2 s ws i 2 s bck i 2 s mlck (optional) v ddd c vddd 100 nf c stabd 1 m f c vdda 100 nf 3.3 v vpa c stab 100 nf c vpa 100 nf c stab 100 nf 12 3 4 56 789 101112 010aaa478 c boot 15 nf c sn 470 pf c sn 470 pf c lc 680 nf c lc 680 nf c boot 15 nf r sn 10 w r sn 10 w c lc 680 nf c lc 680 nf lic s2 f2 s1 f1 15 m h 24 23 22 21 20 19 18 17 16 15 14 13 c vddp c vddp vp out1 + - 6 w to 8 w out2 + - 6 w to 8 w c boot 15 nf c boot 15 nf f2 s2 f1 s1 15 m h lic r sn 10 w r sn 10 w c sn 470 pf c sn 470 pf power in v p = 8 v to 20 v gnd c vddp 220 m f / 25 v r vdda 10 w vpa vp 100 nf 100 nf r staba 1 k w xtall c xtall 18 pf c xtall 18 pf 3.3 v
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 55 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14.4.4 i 2 s master mode and i 2 c control mode fig 16. simpli?ed application diagram for i 2 s master mode and i 2 c control mode tfa9812 adsel1/plim1 out1n out1n boot2p out2p out2p v ddp v ddp out1p out1p boot1p out2n out2n adsel2/plim2 xtalin xtalout v dda(3v3) staba refa v dda test1 v ss1 stab2 v ssp2 v ssp2 boot2n csel gain enable avol powerup cdelay diag stab1 v ssp1 v ssp1 boot1n scl/sfor sda/ms v ddd(3v3) stabd refd test2 data ws bck mclk v ss2 exposed die paddle 36 37 38 39 40 41 42 43 44 45 46 47 48 35 34 33 32 31 30 29 28 27 26 25 enable powerup diagnostic c delay 1 nf c stab 100 nf i 2 c scl i 2 c sda i 2 s data i 2 s ws i 2 s bck i 2 s mlck vddd c vddd 100 nf c stabd 1 m f c vdda 100 nf 3.3 v vpa c stab 100 nf c vpa 100 nf c stab 100 nf 12 3 456789101112 010aaa479 c boot 15 nf c sn 470 pf c sn 470 pf c lc 680 nf c lc 680 nf c boot 15nf r sn 10 w r sn 10 w c lc 680 nf c lc 680 nf lic s2 f2 s1 f1 15 m h 24 23 22 21 20 19 18 17 16 15 14 13 c vddp c vddp vp out1 + - 6 w to 8 w out2 + - 6 w to 8 w c boot 105 nf c boot 15 nf f2 s2 f1 s1 15 m h lic r sn 10 w r sn 10 w c sn 470 pf c sn 470 pf 3.3 v xtall c xtall 18 pf c xtall 18 pf power in v p = 8 v to 20 v gnd c vddp 220 m f / 25 v r vdda 10 w vpa vp 100 nf 100 nf r staba 1 k w
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 56 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 14.5 curves measured in typical application (1) f i = 6 khz (2) f i = 1 khz (3) f i = 100 hz (1) f i = 6 khz (2) f i = 1 khz (3) f i = 100 hz a. v p = 12 v; r l = 2 6 w b. v p = 12 v; r l = 2 8 w (1) f i = 6 khz (2) f i = 1 khz (3) f i = 100 hz (1) f i = 6 khz (2) f i = 1 khz (3) f i = 100 hz c. v p = 15 v; r l = 2 6 w d. v p = 15 v; r l = 2 8 w fig 17. total harmonic distortion-plus-noise as a function of output power 010aaa480 1 10 - 1 10 thd+n (%) 10 - 2 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) (3) 010aaa481 1 10 - 1 10 thd+n (%) 10 - 2 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) (3) 010aaa482 1 10 - 1 10 thd+n (%) 10 - 2 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) (3) 010aaa483 1 10 - 1 10 thd+n (%) 10 - 2 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) (3)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 57 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input a. v p = 12 v; r l = 2 6 w ; p o = 1 w b. v p = 12 v; r l = 2 8 w ; p o = 1 w fig 18. total harmonic distortion-plus-noise as a function of frequency 010aaa484 1 10 - 1 10 thd+n (%) 10 - 2 f (hz) 10 10 5 10 4 10 2 10 3 010aaa485 1 10 - 1 10 thd+n (%) 10 - 2 f (hz) 10 10 5 10 4 10 2 10 3 v p = 12 v; p o = 1 w (1) r l = 6 w 15 m h / 680 m f (2) r l = 8 w 15 m h / 680 m f v p = 12 v; r l = 8 w ; f i = 1 khz (1) 0 db (2) 24 db gain boost fig 19. gain as a function of frequency fig 20. gain as a function of avol 010aaa486 - 1 1 3 g (db) - 3 f (hz) 10 10 5 10 4 10 2 10 3 (1) (2) avol (v) 03 2 1 0.5 1.5 2.5 010aaa487 - 80 - 100 - 60 - 20 - 40 0 g (db) - 120 (1) (2)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 58 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input v p = 12 v; v ripple = 500 mv (rms) reference to ground; no input signal (1) r l = 8 w (2) r l = 6 w v p = 15 v; 20 khz aes17 ?lter (1) r l = 2 8 w (2) r l = 2 6 w fig 21. svrr as a function of frequency fig 22. s/n ratio as a function of output power 010aaa488 - 60 - 40 - 80 - 20 0 svrr (db) - 100 f i (hz) 10 10 5 10 4 10 2 10 3 (1) (2) 010aaa489 70 80 60 90 100 s/n (db) 50 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) a. v p = 15 v; r l = 2 6 w btl; f i = 1 khz b. v p = 20 v; r l = 2 8 w btl; f i = 1 khz (1) t act(th_fold) = 125 c (2) t act(th_fold) = 105 c (3) t act(th_fold) = 90 c fig 23. output power as a function of time time (s) 0 600 480 240 360 120 010aaa490 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3) time (s) 0 600 480 240 360 120 010aaa491 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 59 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input (1) power limiter = 0 db (2) power limiter = - 1.5 db (3) power limiter = - 3 db (4) power limiter = - 4.5 db (1) power limiter = 0 db (2) power limiter = - 1.5 db (3) power limiter = - 3 db (4) power limiter = - 4.5 db a. v p = 12 v; r l = 2 6 w ; f i = 1 khz; thd = 1 % b. v p = 12 v; r l = 2 6 w ; f i = 1 khz; thd = 10 % (1) power limiter = 0 db (2) power limiter = - 1.5 db (3) power limiter = - 3 db (4) power limiter = - 4.5 db (1) power limiter = 0 db (2) power limiter = - 1.5 db (3) power limiter = - 3 db (4) power limiter = - 4.5 db c. v p = 15 v; r l = 2 8 w ; f i = 1 khz; thd = 1 % d. v p = 15 v; r l = 2 8 w ; f i = 1 khz; thd = 10 % fig 24. output power as a function of supply voltage 010aaa492 v p (v) 820 16 18 12 14 10 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3) (4) 010aaa493 v p (v) 820 18 16 14 12 10 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3) (4) 010aaa494 v p (v) 820 16 12 10 14 18 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3) (4) 010aaa495 v p (v) 820 16 12 10 14 18 10 15 5 20 25 p o (w/chan.) 0 (1) (2) (3) (4)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 60 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input v p = 12 v; f i = 1 khz; power dissipation in junction only (1) r l = 2 6 w (2) r l = 2 8 w v p = 12 v; f i = 1 khz; h po = (2 p o ) / (2 p o + p d ) (1) r l = 2 6 w (2) r l = 2 8 w fig 25. power dissipation as a function of output power fig 26. ef?ciency as a function of output power 010aaa496 1 2 3 p (w) 0 p o (w/channel) 10 - 2 10 2 10 10 - 1 1 (1) (2) p o (w/channel) 010 8 46 2 010aaa497 40 60 20 80 100 h po (%) 0 (1) (2) v p = 12 v; p o = 1 w (1) r l = 2 6 w (2) r l = 2 8 w fig 27. channel separation as a function of frequency 010aaa498 - 60 - 40 - 80 - 20 0 a cs (db) - 100 f (hz) 10 10 5 10 4 10 2 10 3 (1) (2)
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 61 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 15. package outline fig 28. package outline sot619-8 (hvqfn48) references outline version european projection issue date iec jedec jeita sot619-8 - - - mo-220 - - - sot619-8 07-01-10 07-01-30 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 1 0.05 0.00 0.30 0.18 7.1 6.9 5.75 5.45 7.1 6.9 5.75 5.45 5.5 5.5 0.1 a 1 dimensions (mm are the original dimensions) hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm b c 0.2 d (1) d h e (1) e h e 0.5 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m 13 24 48 37 36 25 12 1 terminal 1 index area l e h d h c y c y 1 x b a terminal 1 index area d e detail x a a 1 c
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 62 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 16. handling information it is advisable to abide by the normal precautions appropriate to handling mos devices.
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 63 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 17. revision history table 59. revision history document id release date data sheet status change notice supersedes tfa9812_2 20090122 preliminary data sheet - tfa9812_1 modi?cations: ? t ab le 55 dc char acter istics v ih maximum value updated. tfa9812_1 2008/10/30 preliminary data sheet - -
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 64 of 66 nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
tfa9812_2 ? nxp b.v. 2009. all rights reserved. preliminary data sheet rev. 02 22 january 2009 65 of 66 continued >> nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 general features . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 dsp features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 audio data input interface format support. . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 functional modes . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1 control modes . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 key operating modes . . . . . . . . . . . . . . . . . . . . 9 8.2.3 i 2 s master/slave modes and mclk/bck clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3 power-up/power-down . . . . . . . . . . . . . . . . . . 13 8.3.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3.2 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.4 digital audio data input . . . . . . . . . . . . . . . . . . 14 8.4.1 digital audio data format support . . . . . . . . . . 14 8.4.2 digital audio data format control . . . . . . . . . . . 16 8.5 digital signal-processing features . . . . . . . . . . 16 8.5.1 equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5.1.1 equalizer options . . . . . . . . . . . . . . . . . . . . . . 16 8.5.1.2 equalizer band function . . . . . . . . . . . . . . . . . 16 8.5.1.3 equalizer band control . . . . . . . . . . . . . . . . . . 18 8.5.2 digital volume control . . . . . . . . . . . . . . . . . . . 20 8.5.3 soft mute and mute . . . . . . . . . . . . . . . . . . . . 21 8.5.4 output signal and word-select polarity control 21 8.5.5 gain boost and clip level control . . . . . . . . . . . 21 8.5.6 output power limiter . . . . . . . . . . . . . . . . . . . . 22 8.5.7 pwm control for performance improvement . . 22 8.6 class-d ampli?cation . . . . . . . . . . . . . . . . . . . 23 8.7 protection mechanisms . . . . . . . . . . . . . . . . . 23 8.7.1 thermal foldback . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 overtemperature protection . . . . . . . . . . . . . . 24 8.7.3 overcurrent protection . . . . . . . . . . . . . . . . . . 24 8.7.4 overvoltage protection . . . . . . . . . . . . . . . . . . 24 8.7.5 undervoltage protections . . . . . . . . . . . . . . . . 24 8.7.6 overdissipation protection . . . . . . . . . . . . . . . 25 8.7.7 window protection . . . . . . . . . . . . . . . . . . . . . 25 8.7.8 lock protection . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7.9 underfrequency protection . . . . . . . . . . . . . . . 25 8.7.10 overfrequency protection . . . . . . . . . . . . . . . . 25 8.7.11 invalid bck protection . . . . . . . . . . . . . . . . . . 26 8.7.12 dc blocking . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.7.13 overview protections . . . . . . . . . . . . . . . . . . . 26 9i 2 c bus interface and register settings . . . . . 27 9.1 i 2 c bus interface. . . . . . . . . . . . . . . . . . . . . . . 27 9.2 i 2 c bus tfa9812 device addresses . . . . . . . . 27 9.3 i 2 c write cycle description . . . . . . . . . . . . . . . 28 9.4 i 2 c read cycle description . . . . . . . . . . . . . . . 28 9.5 top-level register map . . . . . . . . . . . . . . . . . . 29 9.5.1 interpolator settings and soft mute. . . . . . . . . 31 9.5.2 volume control . . . . . . . . . . . . . . . . . . . . . . . . 31 9.5.3 digital input format . . . . . . . . . . . . . . . . . . . . . 32 9.5.4 equalizer con?guration. . . . . . . . . . . . . . . . . . 32 9.5.5 equalizer settings . . . . . . . . . . . . . . . . . . . . . . 33 9.5.6 pwm signal control . . . . . . . . . . . . . . . . . . . . 35 9.5.7 digital-in clock con?guration. . . . . . . . . . . . . . 36 9.5.8 thermal foldback control . . . . . . . . . . . . . . . . 36 9.5.9 tfa9812 temperature . . . . . . . . . . . . . . . . . . 37 9.5.10 miscellaneous status . . . . . . . . . . . . . . . . . . . 37 9.6 overview of functional control in each control mode . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 39 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42 12 thermal characteristics . . . . . . . . . . . . . . . . . 43 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 13.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . 44 13.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . 47 13.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14 application information . . . . . . . . . . . . . . . . . 49 14.1 output power estimation . . . . . . . . . . . . . . . . 49 14.2 output current limiting . . . . . . . . . . . . . . . . . . 50 14.3 speaker con?guration and impedance. . . . . . 51 14.4 typical application schematics . . . . . . . . . . . . 51 14.4.1 i 2 s slave mode and legacy control mode . . . 52 14.4.2 i 2 s slave mode and i 2 c control mode . . . . . . 53 14.4.3 i 2 s master mode and legacy control mode . 54 14.4.4 i 2 s master mode and i 2 c control mode . . . . . 55 14.5 curves measured in typical application . . . . . 56 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 16 handling information . . . . . . . . . . . . . . . . . . . 62 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 63 18 legal information . . . . . . . . . . . . . . . . . . . . . . 64 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 64 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
nxp semiconductors tfa9812 btl stereo class-d audio ampli?er with i 2 s input ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 22 january 2009 document identifier: tfa9812_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19 contact information. . . . . . . . . . . . . . . . . . . . . 64 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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